1. Field of the Invention
The present invention relates generally to a method and apparatus for accurately locating and positioning electrical or electronic items at identified sites on substrates and, more particularly, to a method and apparatus for accurately batch positioning electronic circuits, components or chips onto identified sites (footprints) on multichip module (MCM) substrates.
2. Description of the Problem and Prior Art
In the fabrication of multichip modules for today's computers, electronic elements or components (e.g., transistors, diodes, capacitors, etc.) are closely integrated into the form of small "chips" which are mounted upon ceramic substrates. Before mounting the chips upon the substrate, the substrate is prepared for the multiple chips by providing it an array of chip sites with each chip site taking the form of a "footprint" or configuration of solder pads which match the electrical connections of the solder pad configuration on each of the respective chips. Typically, the solder pads of the chip are arranged on the same side of the chip as the chip components and may take the form of solder balls which are, after positioning on the substrate, bonded to corresponding substrate pads forming the "footprint".
With the trend toward smaller and smaller chips positioned in multiple form in closer and closer proximity to one another on a single substrate, chip handling and accurate chip placement on its "footprint" or site becomes more and more of a problem, particularly if it is desired to achieve automatic batch chip positioning on the substrate for high throughput. Compounding the problem is the fact that after the chip "footprints" or sites are created on the ceramic substrate, the substrate is fired for hardening and, as a result, a certain degree of shrinkage is introduced into the ceramic. Although the shrinkage within a given substrate is relatively uniform, the shrinkage factor varies considerably from substrate to substrate, thereby causing the chip site coordinates to vary from substrate to substrate.
In addition to variations in shrinkage factor, variations also exist from substrate to substrate in the orientation or alignment of chip sites and their X and Y offsets with respect to the edge of the substrate. These later variations occur as a result of the fact that although the respective location of sites may be positioned relatively accurately from site to site within a substrate, the position of the array of sites with reference to the substrate edge cannot be obtained with the same degree of accuracy. Accordingly, the X and Y coordinate offsets and rotation of the array of sites with respect to the substrate edge, along with the shrinkage factor, must be compensated for before accurate positioning can be obtained.
Various efforts have been made in the prior art to align electronic components, such as chips and the like, for positioning on substrates. Typical of prior art efforts is that described by H. R. Rottman in U.S. Pat. No. 3,581,375 issued June 1, 1971, and assigned to the assignee of the present invention. However, the Rottman system scans both chip and substrate to position one chip at a time and requires manual intervention. Likewise, U.S. Pat. No. 3,840,978, issued Oct. 15, 1974 to Lynch et al and assigned to the assignee of the present invention, describes an alignment system for positioning one chip at a time on a substrate utilizing manual techniques.
Further typifying prior art efforts to align chips and the like to substrates is that described in U.S. Pat. No. 4,125,798, issued Nov. 14, 1978, to Miller. Like Rottman and Lynch et al, Miller describes an arrangement for positioning one chip at a time on a substrate utilizing manual techniques. Another arrangement for positioning one chip at a time is that described by Atchley et al in U.S. Pat. No. 4,116,348, issued Sept. 26, 1978. Although Atchley et al describe a parallel feed arrangement for batch feeding of chips, the chips are picked up one at a time and positioned upon a substrate previously positioned to the proper X-Y location.
Although the prior art describes various arrangements for aligning chips to substrates, none of the prior art describes a high throughput arrangement for aligning multiple chips in a batch mode to a substrate, as described in accordance with the present invention. Gross batch positioning of wafers is described in U.S. Pat. No. 4,108,323 to Charles et al. However, Charles et al do not align their batch of wafers to any substrate arrangement but rather change the spacing between the wafers in accordance with the batch process step being undertaken. Thus, the wafers of the batch are spaced closely in a heat treatment step and then are spaced further apart, for example, in a subsequent chemical processing step.
Not only does the prior art fail to provide an arrangement for batch alignment and positioning of chips to wafers, it also fails to provide any arrangement for making predictions as to X, Y, .theta. and shrinkage factor corrections required to accurately align chips to a substrate in an automatic mode.